Renesas Electronics /R7FA6M3AH /EDMAC0 /FCFTR

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Interpret as FCFTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)RFDO0 (000)RFFO

RFFO=000, RFDO=000

Description

Flow Control Start FIFO Threshold Setting Register

Fields

RFDO

Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.)

0 (000): When 224 ( 256 - 32) bytes of data is stored in the receive FIFO.

1 (001): When 480 ( 512 - 32) bytes of data is stored in the receive FIFO.

2 (010): When 736 ( 768 - 32) bytes of data is stored in the receive FIFO.

3 (011): When 992 (1024 - 32) bytes of data is stored in the receive FIFO.

4 (100): When 1248 (1280 - 32) bytes of data is stored in the receive FIFO.

5 (101): When 1504 (1536 - 32) bytes of data is stored in the receive FIFO.

6 (110): When 1760 (1792 - 32) bytes of data is stored in the receive FIFO.

7 (111): When 2016 (2048 - 32) bytes of data is stored in the receive FIFO.

RFFO

Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.)

0 (000): When 2 receive frames have been stored in the receive FIFO.

1 (001): When 4 receive frames have been stored in the receive FIFO.

2 (010): When 6 receive frames have been stored in the receive FIFO.

3 (011): When 8 receive frames have been stored in the receive FIFO.

4 (100): When 10 receive frames have been stored in the receive FIFO.

5 (101): When 12 receive frames have been stored in the receive FIFO.

6 (110): When 14 receive frames have been stored in the receive FIFO.

7 (111): When 16 receive frames have been stored in the receive FIFO.

Links

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